Digital information handling apparatus



pt 1954 c. A. LAY, JR., ETAL DIGITAL INFORMATION HANDLING APPARATUSOriginal Filed Dec. 30,1955

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United States Patent O 3,150,353 DIGEEAL F JRINIAMGN HANDLING AARATJ5Claims. (Ql. S ill-174) This invention relates to the handling ofinformation in bivalued digital form and more particularly to sensingthe switching of bi-state storage elements from a first to a secondstate. The invention, -roreover, pertains to magnetic registers fordigital information and the sensing of the states of magnetic storagecores.

Magnetic registers have been known to the digital computing art for annumber of years. In one embodiment these registers talre the form ofstepping registers in which two banks of magnetic elements or cores areutilized to store a line or word of digital information. In such astepping register the information is fed serially to the first core in arow and thereafter is stepped sequentially through the cores of the row.

In order to store the information while it is being stepped from onecore to the next, a second line of cores is utilized which acts astemporary storage register for the information being stepped along thefirst row of cores. In this type of device a bit of digital informationis used to set the first core of the first row and is thereaftertemporarily shifted to and stored in the first core of the second rowand hence shifted to the second core of the first row and so forth. Adevice of this type is decribed in a copending application to the sameassignee entitled Magnetic Data Supply Apparatus, invented by Richard H.Fuller and Dudley A. Buck, Serial No. 502,324, new US. Patent 2,987,707.It will be apparent that this type of magnetic register requires in facttwo registers, one of which is active only a small portion of the timeand which is utilized only for temporarily storing the digitalinformation as it is stepped into the register.

When digital information has been stored in the register it isfrequently desirable that the number be read out repeatedly from all thecores in parallel. To accomplish this it is necessary either that theword he read out in such a way as to not destroy the state of the coresin the register or else that some convenient and expeditious way ofrewriting the information in the cores be provided.

Where the core register is to be utilized in digital substractingcircuitry it is also desirable that some means be provided forcomplementing the word which is stored in the register. Thl in binarydigital notation, means reversing t e magnetization state of each of thecores in the register, whatever that state may be. Such a step generallyrequ res relatively complex circuitry.

The general aim of the invention is to realize an improved, compact, andreliable arangement for determin ng when a oi-state storage device isswitched from one state to another by temporarily storing the responseor lack of repsonse in a semi-conductor device having a slow recoveryresistance characteristic.

It is another object of this invention to provide a simple ander'iicient means of controlling magnetic core registers without the needfor additional cores to act as temporary storage media.

It is similarly the object of this invention to provide a single linestepping register which does not need a second register of cores fortemporary storage.

It is further the object of this invention to provide a simple andimproved method of automatically resetting ice a core, which is reversedin the state or direction of its residual magnetization by a readoutcurrent, back to its original state.

It is an additional object of this invention to provide a simple andeffective circuit for reversing the state of each core in a register andthereby complementing the binary number contained in the register.

It is the feature of this invention that these desirable objectives maybe achieved through the use of a semiconductor device, such as a crystaldiode, having particular characteristics making it undesirable for manyapplications, while at the same time providing very usefulcharacteristics for use in the subject invention.

This invention will be more easily understood upon reference toexemplary embodiments illustrated by the accompanying drawings, inwhich:

FIGURE 1 illustrates a basic diode amplifier circuit utilized in thisinvention.

FIG. 2 illustrates a stepping register circuit utilizing this invention.

FIG. 3 illustrates a non-destructive readout circuit constructed inaccordance with this invention.

FIG. 4 illustrates a complementing circuit utilizing this invention.

While the invention has been shown and will be described in some detailwith reference to particular embodirnents thereof, there is no intentionthat it thus be imited to such detail. On the contrary, it is intendedhere to cover all modifications, alternatives and equiva lents fallingwithin the spirit and scope of the invention as defined by the appendedclaims.

The operation of this invention depends upon the characteristics ofsemi-conductor devices of the type having what is known as a slowrecovery of a normally high resistance, after such resistance has beenlowered by current flow. in their simplest form, such devices may beasymmetrically conductive diodes of the P-N junction type. When such adiode is conducting in the forward direction the applied voltageprovides a steady supply of current ca riers. The forward impedance orresistance of the diode is relatively low. Without going unnecessarilydeeply into the special concepts involved in semi conductor circuitry itmay be said that a diode passing a forward current is characterized by alarge number of holes or minority carriers, flowing into the N region ofthe diode from the P region of the diode. These so-called holes have alifetime which may vary from fractions of a microsecond to tens ofmicroseconds for difierent types of diodes. It the diode has beenconduct ing in the forward direction for a time which is large withrespect to the hole lifetime then the hole density reaches a steadystate distribution across the diode.

When voltage applied to thediode is switched to the so-called reversebias direction from the forward bias direction, these minority carriersmust disappear before the diode will fully oppose reverse curernt flow,i.e., reach its steady state value of back resistance. As these minoritycarriers are disappearing, a transient phenomenon of high current flowin the reverse bias direction takes place. In other words, the normallyhigh back resistance is temporarily relatively low. At first thisreverse current is very large and in fact is limited by the externalparameters, e.g., voltage and resistance, of the circuit with which thediode is connected. As the holes are redistributed'the back resistanceof the diode increases until all of the excess holes have disappearedand the back resistance assumes its static, relatively high value. Ineffect, these holes constitute a temporarily stored current which may beswept out by the application of a reverse bias voltage. Theabove-described operation of a diode is described in The National Bureauof Standards Technical News Bulletin, vol. 38, No. 10. It should benoted covery time and the other of which has a relatively rapid recoverytime. The circuit as here shown employs a slow recovery diode 19together with a fast recovery diode 12. The resistance 14 ties themid-points of the two diodes to ground or other point of referencepotential. The output is taken from the mid-point of the two diodes.Throughout the drawing, slow recovery diodes are designated by thesymbol (S.R.) following the reference characters applied thereto.

The slow recovery diode 19 is capable of storing energy for a short butuseful period of time (e.g., one or two microseconds). The 1N91 type ofgermanium junction diode has proven satisfactory in this regard andother diodes particularly the diffused and grown junction types (forexample, Western Electric 1784) have suitable characteristics for use incircuits wherein the hole storage property of the semi-conductor isutilized. The diode 12, on the other hand, is a fast recovery diodewhich is assumed for the purposes of these circuits to be a truebivalued element not involving the storage of current. its

recovery time may be of the order of hundredths of a. I microsecond. Apoint-contact diode, for example of the 1N38A type, is suitable for useas diode 12.

Assuming that a voltage is applied to terminals 16 and 18, making thelatter positive with respect to the former,

current in the forward direction is supplied over a termifor the diode10,. there will be a large temporary current fiow reversely through thediode 19 before it reaches its high reverse resistivity state. Thiscurrent will be blocked by the fast recovery diode .12 and will eitherbe passed through the resistor 14 to ground or out through any otherconductive path leading from the output terminal In accordance with thepresent invention, the state of a bi-state. storage element isdetermined by coupling a slow recovery semi-conductor device to theelement by means which produce current flow in a low resistance paththrough the device in response to switching of the element from itsfirst to its second state, thereby creating minority carriers within thedevice. The magnitude of resistance presented by a reverse conductionpath in the device is sensed by applying a reverse voltage thereto. Ifthe back resistance is high, substantially no reverse current occurs,indicating that the. storage element has a not been switched to itssecond state. just prior to the the back resistance is low, appreciablereverse current occurs, indicating that the element has just beenswitched to its second state. By timing the application of a signal.which tends to switch the storage element from thefirst to the secondstate and the application of the reverse voltage, the storage element isknown to have been in its first state prior to the .signal ifappreciable reverse currentoccurs. And such current may be used,directly or indirectly, to change the state of another, or the same,

. storage element.

' There is illustrated by reference to FIG. 2 a particularly valuableembodiment of this basic circuit in a novel magnetic shift registerhaving'half the usual number of fcores'and certain other very 'desirablecharacteristics 60 application of the reversejvoltage. On the otherhand; if

i as follows.

'and back to ground at the source 50.

. which Will appear as this circuit is explained. The cores 22, 24, and26 constitute storage elements capable of residing in and being switchedto either of two states, such cores being made of magnetic materialhaving a substantial residual magnetization characteristic, as is wellknown. The two states of each storage element or core are represented bythe two senses or directions of residual flux therein, and switchingfrom one state to the other occurs when magnetornotive forces of theappropriate sense are applied. The first core 22 carries the inputwinding 28 which is utilized to set the core 22 in accordance with theincoming bit of digital information. Each core in addition carries atransfer or readout winding 30, 32 and 34 and these windings areconnected in series by lead 35 to a current pulse source 38 which iscapable of supplying a current pulse which thus creates a magnetomotiveforce to all cores tending to set them in the second state or directionof residual flux. The input and trans fer windings constitute controlwindings which are used to set the core to a desired state of residualmagnetization.

The cores 22 and 24 are linked together by a connect ing circuit similarto that shown in FIG. 1. This includes means for producing current in aforward direction through a slow recovery diode 48, coupled to an outputwinding 45 on the core 22, whenever the core switches from its first toits second state. The core 22 carries an output winding 40, one terminalof which is connected to ground, and the other terminal of which isconnected to the quick recovery diode 42. The second core 24 carrieswhat may be broadly considered a utilization device, i.e., an inputwinding 44 one terminal of which is connected through the resistance 46to ground and the other terminal of which is connected to the oppositeside of the diode 42 from the widing 40. The slow recovery or temporarystorage diode 48 also connects the input winding 44 and the output sideof the quick recovery diode to the voltage pulse source 50. It will beseen that a series circuit is established from ground through the outputWinding 40, the similarly poled diodes 42' and 48, Also a series circuitis established across the slow recovery diode 48, leading through theinput winding 44 and the resistance 46 to ground, and from groundthrough thesource 50 to the opposite side of the diode 48. In otherwords, the utilization device or input winding 44 is connected inparallel with the series combination of the output winding forwarddirection conducting from the winding 54 to the.

voltage pulse source 51).

Appropriate pulse timing is achieved by use of the delay element 62which may be a monostable-multivibrator or other fixed delay circuitwhich energizes the voltage source 50 a predetermined length of timeafter the current pulse source 33 has been energized This length.

of time must produce a reverse bias voltage from source '50 at a timeafter the output from winding 40 (for example) which is longer than therecovery time of the quick recovery diode 42 and shorter than therecovery time of the slow recovery or storage diode 48.

The voltage source 59 triggered by the multivibrator I may forconvenience be a blocking oscillator and the current source 38 maybe apentode which receives its grid These signal from another monostable.multivibrator. elements constitute well known standard components in theelectrical art and numerous engineering alternatives could readily beprovided. 7

.The operation of the circuit illustrated in FI GPZ is Core 22 can beset by theinput winding 281to either of two states of residualmagnetizationpone corresponding tothe-st'orage of a digital Ofand theother corresponding to the storage or" a digital 1. Assuming that thecore 22 is set to a state which corresponds to the storage of a digital1, a transfer current pulse from the source 33 over lead 35 to energizethe winding 34) will reverse the state of the core back to thatcorresponding to a digital O and at the same time will result in avoltage pulse of predetermined polarity being induced in the winding 40.The polarity of the voltage pulse is chosen so that output current willpass forwardly through the diode 42 and out through the short circuitpresented by the diode 48 which conducts in its forward direction,having very little resistance. This current will have the efiect ofcharging the diode 48. The same pulse of current over lead 35 which isutilized to drive the winding 3% (and windings 32 and 34) is delayed bythe element 62 for a short interval (e.g., a few tenths of amicrosecond) to permit the cores to reverse their state and then isutilized to trigger a voltage source 58, which thereby applies a voltagein the reverse bias direction to the slow recovery diodes 48 and 60.

If the core 22 has just been switched to the stat this reverse biasvoltage applied to diode 48 will result in a large surge of current inthe reverse direction through this diode, since the latter will be in acondition of temporarily lowered back resistance. This current will beblocked by the quick recovery diode 42 and will therefore flow throughthe winding 44 on core 24 in a direction which will result in settingcore 24 to that state or direction of residual magnetization whichcorresponds to the storage of a digital 1. By this means the digital 1which was formerly stored in core 22 is now transferred to core 24.Similarly, at the same thne that the content of core 22 was read out,the content of core 24 was read out by the readout current applied tothe winding 32. Thus the contents of cores 22 and 24 were read outsimultaneously and stored as the states (i.e., high or low backresistance depending upon whether cores 22 and 24 were originally in the0 or 1 state) of the slow recovery diodes 48 and 60. A voltage pulse inthe reverse bias direction on these diodes 48 and 6t) timed a shortinterval after the current pulse supplied by source 38 will result insetting cores 24 and 26 to correspond to the previous states of cores 22and 24, respectively. By this means digital information is stepped intothe register which may contain any number of cores serially connected inthis manner.

Of course, if the core 22 is in the b nary 0 state when an interrogatingpulse is supplied to the readout winding 30, then no reversal of flux inthat core occurs. No voltage is induced in the output winding 49, so nocurrent flows through the diodes 42 and 48. Thus, when the delayedreverse voltage is applied to the diode 48, the latter contains no holesand will not conduct. No current can flow through the winding 44 so thatthe second core 24 is left in the 0 state, which is the state created bythe preceding current pulse in its readout winding 32. It will thus beapparent that the binary number or state (whether it be 0 or 1) of eachcore is shifted to the next succeeding core in response to eachinterrogating pulse from the source 38.

In the experimental register utilizing this design the conventional1N38A diode proved satisfactory for the quick recovery diodes 42 and 58,while the 1N91 type was utilized as the slow recovery diodes 48 and 60.It was found that the current from the source 38 should be of the orderof .8 ampere, the current through the diodes 48 and 649 of the order of.15 ampere, and the reverse bias voltage of the order of 100 volts.

In the experimental stepping register having current and voltagemagnitudes of this order the input windings were 30 turns, the outputwindings 20 turns and the w'md- ,ings used to drive each of the coressimultaneously turns. The timing means was set to produce the reversebias voltage on the slow recovery diodes at an interval of approximately.1 microsecond after the forward pulse passed through this diode. Theoutput current from the core through the diode produced a pulse ofapproximately 2 microseconds duration and the reverse current had aduration of approximately 1 microsecond. This reverse current was of theorder of one-third the magnitude of the setting current. The registerwas able to circulate a stored digital word at a 100 kilocycle rate withno deterioration in the switching behavior of the cores or diodes. Itrequired half the input power and half the number of diodes and coresutilized in the standard two core per digit register used in mostdigital computing machinery.

While the stepping register construction above described is believed toconstitute the most widely useful and general form of this invention theconstruction can be varied or added to in a number of ways to providediode controlled magnetic registers having somewhat differentcapabilities when used as computer elements. For example, in digitalmultiplication it may be desirable to store a digital number or word ina bank of cores and repeatedly read the contents of the register topermit the addition of the number to itself a large number of times,thereby accomplishing multiplication. In such a register it is eithernecessary to rewrite the readout information each time that it is usedor else utilize some nondestructive means of readout. It is possible bythe use of the above-described diode control to accomplish an automaticrewrite of information which permits a speed of operation andconvenience of construction comparable to a true nondestructive readout.Such a register constituting one en bodiment of the invention is shownin FIGURE 3.

By reference to FIGURE 3 it will be seen that the three cores 7t}, 72and 4 carry the transfer windings "76, 78 and 3% which are formed fromlead 82 and driven by the current source 84. The term transfer is usedto indicate transfer of the information to slow recovery semi-conductordevices for temporary storage. For purposes of simplicity, separateinput windings 36, S8 and 9d are illustrated for each core. The steppingregister construction described above could be used, but wouldcomplicate the drawings. Assuming that input currents on the threeread-in windings 86, SS and 5d) are used to set the cores to storedigital information, the problem remains of repeatedly reading out ofthe cores and rewriting said information back into them.

To accomplish this result the output windings 92, 9- and 96 are carriedby each core. These windings are connected at one end to ground and areconnected at the other end to the output terminals 98, 1% and 192. Theoutput windings 92, E4 and 96 feed the networks consisting of quickrecovery diodes 19 i, 1% and 1%, slow recovery diodes 116, 112 and 11and resistors 1E6, 11 and 12". Each resistor is connected between themidpoint junction of the two diodes and the terminals at one end ofcorresponding reinsertion or reset windings 122, 124- and 126 which maybe viewed as utilization devices.

The operation of these networks is identical with the operationdescribed with respect to FEG. 2, except that the. energy stored in theslow recovery diodes 110, 112 and 114, instead of being used to set thestate of the next core in the register, is used to reset the state ofthe core from which the information was read. Thus a current pulsesupplied on lead 82 and passing through the transfer windings 76, 78 and853 will result in a current in the output windings 92, 94 and if thecorresponding cores stored a digital 1. This will set the slow recoverydiodes 119, 112 and 114. The same current pulse applied to line 82 isdelayed by the delay element 139 and utilized to trigger a voltage pulsefrom the voltage source 132. This positive voltage will be applied tothe lead 134- which is connected to the reverse bias side of the diodes11%), 112 and 1 4. If any of these diodes have been set by the readingout of a digital 1 from the cores 7%, 72 or 74, the voltage applied inthe reverse direction to them will result in a current surge through thereset windings 122, 124

and 126, thereby restoring the information to the register. additionaloperation which is made possible by this invention and which isdesirable, for example, in a i core register being used for subtractionis the process of complementing the register.

This involves reversing the state of each core in the register whetherit is in the state denoting the storage of a digitall or the statedenoting the storage of'a digital 0. The apparatus for achieving thisresult is shown in FIG. 4.

The complementing circuit in FIG. 4 illustrates three cores 150, 152 and154. These cores may be set in the desired state either by a step-inform of register as de i scribed by reference to FIG. 2 or by individualsetting windings as described by reference to FIG. 3. For purposes ofsimplicity in explanation the input windings to the cores of FIG. 4 havebeen omitted and it will be asslow recovery diodes 172, 174 and 176 arecoupled to the respective output windings 184, 186, 188 by completingthe loop formed partially by the winding and the resistor on each core.

' The current pulse source 164, as in preceding instances,

- drives a delay element 173 and this element in turn drives "anothersimilar current source 18% as distinguished from a voltage source inFIGS. 2 and 3. Current from the source 18%} flows through either eachslow recovery diode or its associated output winding and seriesresistor, de-

pending upon whether or not that diode has been previously set. 7

Let it be assumed that'the core 152 is in a statedenoting the storage ofthe digital 1 and that this state is reversed by the application of adriving current to the lead 162 from the source 164. Let it also beassumed that the cores 150 and 154 are in the state denoting the storageof a digital and that a current pulse supplied to lead 162 and hence tothe transfer windings 156 and 160 on these two cores will have no elfecton the state of residual magnetization and therefore no output currentwill be created in the output windings of these cores. The'sense of theoutput winding from core 152 must be chosen to pass the output currentin the forward direction through the diode 174.

The forward current through the diode 174 will leave it in a conditionto conduct current in the reverse bias direc tion for a limited periodof time as in the above-described circuits. In addition, the very factthat this diode 174 is set to carry current in the reverse biasdirection means that the residual state of magnetization of the core 152has been reversed in the transfer or readout process; On the other hand,the cores 150 and 154 have been unchanged and the diodes 172 and 176associated with these cores are not set to pass current in thereverse'bias direc- ;tion. Shortly after the readout from the cores hasbeen accomplished, the pulse from the source 164 delayed by the element178 is utilized to trigger the current pulse source 180 to apply apositive reverse current to the lead 182. The result will be a currentflow through the diode 174, and no current flow through the outputwinding 186.

I the winding 158. However, the diodes 172 and 176 will block thepassage of current and the'current will therefore flow through theoutput windings 184 and 188 and will act -to reverse (i.e., set to 1)the state of scores 151) and 154 which were unchanged by the transfer orreadout pulse applied to lead 162.

By the above-described means, the driving lead 162 is.

utilized to change all of the cores which were in one state of residualmagnetization and at the same time charge the the cores in the registerand thereby achieve a complement of the digital word which wasoriginally stored in the register. Implicit in the foregoing descriptionis the requirement that the timed pair of pulses on leads 162 and 182should be delayed or spaced apart in time less than the recovery time ofthe slow recovery diodes 172,.

It will be obvious from a consideration of the above circuits that theymay be combined on a single core register to achieve a stepping registerin which the information can be read out repeatedly with an automaticrewrite circuit as described in FIG. 3, and in which a stored number canbe complemented by a reversal of each of the cores in the registerwhenever that step is necessary. The principal engineeringconsiderations involved in utilizing all of these circuits in the samecore register is that each winding on the core represents an additionalload and therefore a register containing a large number of windings oneach core will req ire relatively heavy driving currents. Furthermore,the output pulses from the cores in such an instance must be strongerthan in the case where each core carries a more limited number ofwindings.

The above-described invention discloses novel and useful circuit meanswhereby a bi-state storage element and a slow recovery semi-conductivedevice may be combined to achieve highly valuable characteristics. Theinformation which may be stored permanently as the residual fluxdirection within the magnetic elements may be temporarily stored as thedistribution state of the holes in the slow recovery semi-conductordevices. With proper tirn ing of the energy sources the informationtemporarily stored in the semi-conductor devices may be read out to thesame or other cores to achieve the desired type of the combinationcomprisinga bi-state magnetic core having substantial residualmagnetization characteristics and in which the state of the core isrepresented by the direction of residual magnetization of thecore; aseries circuit including an output winding on said core, a fast recoveryi diode, a slow recovery diode, and a pulse source; said diodes bothbeing poled to conduct forward current in response to 'the voltageinduced in said output winding when said core switches from a firststate to the second 'tive force to said core tending to switchthe'latter to said second state; and said pulse source including meansfor applying areverse voltage-to said slow recovery diode with a shortdelay after termination of said magnetomo tive force; so that currentflows reversely throughsaid slow recovery diode and thence through saidutilization Idevice only when said core was in said first state prior toapplication of said magnetomotive force, and such current is blockedbysaid fast recovery diode from passagethrough said output winding. V f 12. In apparatus for handling binary digital information,

i the combinationc omprising a bi-state magnetic core having substantialresidual magnetization characteristics and in which a binary l or'0isstored by residu'al magnetism in one direction or the other;'atransfer winding and an output winding on said core; a series circuitincluding said output winding, 2. fastrrecovery diode,a slow recovery.

diode, and a pulse source; said diodes both being poled to conductforward current response to the voltage induced in said output windingwhen said core switches from the 1 to the 0 state; a utilization deviceconnected in parallel across the series combination or said outputwinding and said fast recovery diode; means for applying a current pulseto said transfer winding tending to drive said core to its 9 state; andmeans for can 'ng said pulse source to generate a voltage pulse with ashort delay after said current pulse and with a polarity tending tocause reverse current fiow through said slow recovery diode, whereby acurrent pulse flows through said utin ation device only if said core hasjust switched to the 0 state and current flow through said outputWinding due to said voltage pulse is blocked by said fast recoverydiode.

3. A diode controlled magnetic stepping register comprising a pluralityof oi-state magnetic cores having substantial retentivit an inputwinding for each core, an output winding for each core, a transferwinding for each core, a fast recovery diode and a slow recovery diodein series with each of said output windings and poled to conduct forwardcurrent in response to the voltage induced in the corresponding outputwinding when the corresponding core switches from a first state to thesecond state, a pulse source, each series combinatio r formed by oneoutput winding and the two diodes associated therewith being connectedin a complete series circuit through said pulse source, means connectiueach of said input windings except the first one in parallel with theseries combination of the output winding and fast recovery diode for thepreceding core, means for simultaneously applying current pulses throughall of said transfer windings in a direction tending to cause switchingof all of said cores to said second state, and means for causing saidpulse source to generate a voltage pulse with a short delay after saidcurrent pulses and tending to cause reverse current flow through saidslow recovery diodes, whereby the state of each core is transferred tothe next succeeding core and said fast recovery diodes prevent reversecurrent flow through said output winch "s.

4. In apparatus for handling binary digital information, the combinationcomprising a bi-st te magnetic core having substantial retentivity; atransfer winding, an output winding, and a reset winding on said core, aseries circuit including said output winding, 21 fast recovery diode, aslow recovery diode, and a pulse source with said diodes both poled toconduct forward current hi response to the voltage induced in saidoutput winding when said core is switched from the first state to thesezond state, said reset winding being connected in parallel with theseries combination of said output winding and last recovery diode, meansfor applying a current pulse to said input winding tending to switchsaid core to said second state, means for causing said pulse source togenerate a voltage pulse with a short delay after said current pulse andwhich tends to produce reverse current through said slow recovery diode,such reverse current passing through said reset winding but beingblocked by said fast recovery diode from passage through aid outputwinding, said reset winding being poled such that the said reversecurrent passed therethrough switches said core from said second to saidfirst state.

5. In apparatus for handling binary digital information, the combinationcomprising a bi-state magnetic core having substanital retentivity, andrepresenting a l or a 0 by the direction of residual flux therein, atransfer winding and an output winding on said core, a slow recoverydiode connected in parallel with said output winding and poled toconduct forward current in response to the voltage induced in saidoutput winding when said core switches from the first state to thesecond state, said diode having a predetermined recovery time followingforward conduction and during w ich it conducts appreciable reversecurrent in response to a reverse voltage thereacross, a pulse sourceconnected in series with said diode and adapted to generate voltagepulses tending to produce reverse current through said diode, means toapply at current pulse to said transfer winding tending to switch saidcore to said 0 state, and means for activating said pulse source with ashort time delay after said current pulse, said time clay being lessthan said diode recovery time, whereby said diode shunts currentresulting from said voltage pulse around said output Winding if saidcore was initially in the 1 state and forces current resulting from saidvoltage pulse through said output winding to set said core to the 1state if it was initially in the 0 state, thereby to complement thebinary information held in the core.

References tilted in the file of this patent UNETED STATES PATENTS OTHERREFERENCES Handbook or" Semiconductor Electronics (Hunter), published byMcGraw-l-Iill, 1956. (Chapter 15, pages 49 and 50 relied on.)

1. IN APPARATUS FOR HANDLING BINARY DIGITAL INFORMATION, THE COMBINATIONCOMPRISING A BI-STATE MAGNETIC CORE HAVING SUBSTANTIAL RESIDUALMAGNETIZATION CHARACTERISTICS AND IN WHICH THE STATE OF THE CORE ISREPRESENTED BY THE DIRECTION OF RESIDUAL MAGNETIZATION OF THE CORE; ASERIES CIRCUIT INCLUDING AN OUTPUT WINDING ON SAID CORE, A FAST RECOVERYDIODE, A SLOW RECOVERY DIODE, AND A PULSE SOURCE; SAID DIODES BOTH BEINGPOLED TO CONDUCT FORWARD CURRENT IN RESPONSE TO THE VOLTAGE INDUCED INSAID OUTPUT WINDING WHEN SAID CORE SWITCHES FROM A FIRST STATE TO THESECOND STATE; A UTILIZATION DEVICE CONNECTED IN PARALLEL WITH THE SERIESCOMBINATION OF SAID FIRST RECOVERY DIODE AND SAID OUTPUT WINDING; PULSEMEANS FOR APPLYING A MAGNETOMOTIVE FORCE TO SAID CORE TENDING TO SWITCHTHE LATTER TO SAID SECOND STATE; AND SAID PULSE SOURCE INCLUDING MEANSFOR APPLYING A REVERSE VOLTAGE TO SAID SLOW RECOVERY DIODE WITH A SHORTDELAY AFTER TERMINATION OF SAID MAGNETOMOTIVE FORCE; SO THAT CURRENTFLOWS REVERSELY THROUGH SAID SLOW RECOVERY DIODE AND THENCE THROUGH SAIDUTILIZATION DEVICE ONLY WHEN SAID CORE WAS IN SAID FIRST STATE PRIOR TOAPPLICATION OF SAID MAGNETOMOTIVE FORCE, AND SUCH CURRENT IS BLOCKED BYSAID RECOVERY DIODE FROM PASSAGE THROUGH SAID OUTPUT WINDING.